When making a CMOS device that includes metal gate electrodes, a replacement gate process may be used to form gate electrodes from different metals. In that process, a first polysilicon layer, bracketed by a pair of spacers, is removed to create a trench between the spacers. The trench is filled with a first metal. A second polysilicon layer is then removed, and replaced with a second metal that differs from the first metal.
In such a replacement gate process, the first and second polysilicon layers (to be replaced with metal) are etched polysilicon layers that define the gate lengths for the subsequently formed metal gate electrodes. In a particular application, it may be desirable to create metal gate electrodes with 45 nm (or shorter) gate lengths. It may not be possible, however, to form an etched polysilicon layer with a width of about 45 nm (or less) that is suitable for high volume manufacturing using conventional photolithographic techniques.
While it may be difficult to form extremely thin etched polysilicon layers, any success in doing so may raise another problem—if those patterned polysilicon layers have substantially vertical side walls. After removing such a patterned polysilicon layer, it may be difficult to uniformly coat the sidewalls of the resulting trench with various materials. In addition, it may not be possible to completely fill such a trench with metal, as voids may form at the trench center.
Accordingly, there is a need for an improved method for making a semiconductor device that includes metal gate electrodes. There is a need for a method for generating a patterned sacrificial structure that enables a gate length of 45 nm (or less), while having a profile that facilitates metal gate electrode formation. The present invention provides such a method.
Features shown in these figures are not intended to be drawn to scale.